Regviz

NXP Semiconductors /MK66F18 /SystemControl /SHCSR

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Interpret as SHCSR

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https://regviz.com/r/NXP Semiconductors/MK66F18/SystemControl/SHCSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)MEMFAULTACT 0 (0)BUSFAULTACT 0 (0)USGFAULTACT 0 (0)SVCALLACT 0 (0)MONITORACT 0 (0)PENDSVACT 0 (0)SYSTICKACT 0 (0)USGFAULTPENDED 0 (0)MEMFAULTPENDED 0 (0)BUSFAULTPENDED 0 (0)SVCALLPENDED 0 (0)MEMFAULTENA 0 (0)BUSFAULTENA 0 (0)USGFAULTENA

BUSFAULTPENDED=0, MEMFAULTENA=0, PENDSVACT=0, SVCALLPENDED=0, MONITORACT=0, BUSFAULTENA=0, SYSTICKACT=0, USGFAULTENA=0, MEMFAULTACT=0, USGFAULTPENDED=0, BUSFAULTACT=0, SVCALLACT=0, USGFAULTACT=0, MEMFAULTPENDED=0

Description

System Handler Control and State Register

Fields

MEMFAULTACT

no description available

0 (0): exception is not active

1 (1): exception is active
BUSFAULTACT

no description available

0 (0): exception is not active

1 (1): exception is active
USGFAULTACT

no description available

0 (0): exception is not active

1 (1): exception is active
SVCALLACT

no description available

0 (0): exception is not active

1 (1): exception is active
MONITORACT

no description available

0 (0): exception is not active

1 (1): exception is active
PENDSVACT

no description available

0 (0): exception is not active

1 (1): exception is active
SYSTICKACT

no description available

0 (0): exception is not active

1 (1): exception is active
USGFAULTPENDED

no description available

0 (0): exception is not pending

1 (1): exception is pending
MEMFAULTPENDED

no description available

0 (0): exception is not pending

1 (1): exception is pending
BUSFAULTPENDED

no description available

0 (0): exception is not pending

1 (1): exception is pending
SVCALLPENDED

no description available

0 (0): exception is not pending

1 (1): exception is pending
MEMFAULTENA

no description available

0 (0): disable the exception

1 (1): enable the exception
BUSFAULTENA

no description available

0 (0): disable the exception

1 (1): enable the exception
USGFAULTENA

no description available

0 (0): disable the exception

1 (1): enable the exception

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data